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Publication

Power modeling of CMOS digital circuits with a piecewise linear model

Liu, Cheng Chih
Abstract
Scope and Method of Study:
This paper presents the average power modeling of CMOS digital circuits with a piecewise linear (PWL) model. The innovation of the piecewise linear model in the average power evaluation against previous power models is to include, for the first time, the effects of the first-order channel capacitive currents into a power calculation. Also, the model in the evaluation of the average power supply current predicts the currents contributed to the short-circuit power, dynamic power, and switching power of parasitic capacitances. A first-order channel storage charge model is derived to compute the power consumption caused by the nonlinear parasitic capacitances in a transistor channel. The PWL modeling of average power was validated by comparing SPICE average power simulation from the power supply current. The proposed model was validated with a submicron CMOS 0.5 um process and a deep submicron 0.18 um process to test its portability as a technology-independent model.
Findings and Conclusions:
The simulation discrepancies were found when the SPICE simulating the average power dissipation from the power supply current and the average power consumed by the devices in the same circuit. The average power consumed by the devices in a circuit is more than provided by the power supply current. The discrepancies come from the zero order quasi-static SPICE transistor model, which computes the instantaneous power from the zero-order quasi-static transistor current and multiplied by its drain-source voltage. It has been well defined that the BSIM is a charge-conserving transistor model, so the average power dissipated by the power supply current into the circuit is the true power in SPICE which was used to test the accuracy of the PWL model. The PWL approximation to the average power of an inverter gate and a two-input NAND gate with various transistor sizes and loads were within 3 to 5% averaged error of SPICE for fast inputs and within 10% for slow inputs. Complex OAI gates were also verified with the same range of accuracy.
Date
2007-05