Johnson, Louis G.Qayum, Mohammad Abdul2014-04-172014-04-172010-07-01http://hdl.handle.net/20.500.14446/10263The main focus of this thesis is to design a MIPS Instruction Set Simulator (ISS) for multicore computer architecture research. This MIPS ISS is tested thoroughly for each instruction and by long test benches. Usual ISS works in a purely functional way unlike real hardware, this ISS is designed at a level more abstract than RTL but closer to real processor which will be easy to interface with other cores, caches and micro-architectural parts.application/pdfCopyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material.textcycle accurateisaissmipsmulticoresystemc`