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Harmonic Mitigation in Dc-Ac Conversion by Utilizing Multi-Level Inverters and Its Application to Pv Systems for Grid Interconnection

Abid, Fahad Hassan
Abstract
Small (0.2-50 kW) and medium (50-1000 kW) PV systems typically utilize square wave inverters for DC-AC voltage conversion. The output voltage of square wave inverters consists of two voltage levels VDC- and VDC+. The square wave outputs are filtered to obtain a sinusoidal waveform before interconnection to the electric grid. While the simplicity of this approach makes it a popular choice, the voltage harmonics of the inverter output require a significant amount of filtering to obtain an acceptable sinusoidal waveform. Lowering voltage harmonic content can significantly lower filtering requirements and the need to invest in bulky filtering equipment.Total Harmonic Distortion (THD) for a square wave inverter is 48.34%; use of a multilevel inverter can significantly reduce this value. The first part of this thesis summarizes several harmonic minimization techniques for multilevel inverters. An equal angle approach can be used to decrease THD to as low as 12%. Elimination of selected harmonics can be used to completely eliminate select low order harmonics and their integer multiples, and reduce THD to below 12% for a 7-level inverter. A THD minimization approach can be used to lower harmonics to below 17% for a 5-level inverter. These results can be achieved without using Pulse Width Modulation (PWM), which is unsuitable for high power applications due to high switching frequency requirements.The second part of this thesis presents the application of multilevel inverters for the interconnection of PV systems to the electric grid. The main principle behind the strategy is designing a separate DC bus for each voltage level to which solar panel modules and a battery backup system are connected. Each DC bus will act as a DC voltage source for the multilevel inverter.Design recommendations will be limited to 7-level inverters since higher level inverters are impractical due to the cost of additional components. A scheme with 3rd order harmonic elimination with THD reduced to 11.82% is presented. A scheme which simplifies equalizing voltage stress by using the equal angle approach with THD reduced to 25.47% is also presented.
Date
2013-07-01
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